TimeSpeakerTopic

Thursday, 16 July 2016
TimeSpeakerTitle
09:20Deepak D'SouzaOpening remarks
Model-Checking and Decision Procedures
09:30Ashutosh GuptaModel Checking Gene Regulatory Networks
10:15Akash LalDAG Inlining: A Decision Procedure for Reachability-Modulo-Theories in Hierarchical Programs
11:00Tea
11:30Prakash SaivasanVerification of concurrent recursive programs with shared memory
Logic
12:15Harsh BeoharOpen maps in concrete categories and branching bisimulation for prefix orders
13:00Lunch
14:00S P SureshThe complexity of disjunction in intuitionistic logic
Program Analysis
14:45Shrawan KumarA New Slicing Concept for Scalable Property Checking
15:30Tea
16:00Kumar MadhukarProof Spaces for Unbounded Parallelism
16:45Prahlad SampathFormal Analysis using MATLAB/Simulink
17:30Nishant SinhaSimplifying Web Programming

Friday, 17 July 2015
TimeSpeakerTitle
Program Verification
09:30Kiran KumarEnabling Shift-Left through FV Methodologies on Intel Graphics Designs
10:15Kamal LodayaRegular Expressions, Sequents and Admissibility of Cut
11:00Tea
11:30Sabuj Kumar JenaLearning Quantified Invariants
12:00Snighda AthaiyaEventual Consistency
Automata and Grammars
12:30Dharani ClementFilling the Three Dimensional Space by Tetrahedra
13:00Lunch
14:00Namit ChaturvediAutomata Classes for Recognizable Languages of Infinite Mazurkiewicz Traces
15:30Tea