Time	Speaker	Topic
Tuesday, 12 July 2011
14:00-15:00	Madhavan Mukund, CMI	The decidability frontier for Petri Nets
15:00-15:30	Tea
15:30-16:30	M Praveen, IMSc	Model-checking finite and infinite state systems
16:30-17:15	S Krishna, IIT Bombay	Construction of Signal Automata for MTL[U,S]
19:30-21:00	Workshop Dinner
Wednesday, 13 July 2011
09:30-10:30	Swarup Mohalik, GM	Verification of end-to-end Latency in embedded systems
10:30-11:00	Kumar Madhukar, TRDDC	dL and KeYmaera : Towards Verification of Hybrid Systems
11:00-11:30	Tea
11:30-12:30	Supratik Chakraborty/Abhishek Sankaran, IIT Bombay	Syntax vs Semantics in First-order Logic: Los Tarski Theorem and its Variants for Finite Structures
12:30-14:00	Lunch
14:00-14:30	Prateek Karandikar, CMI	Cutting through regular post embedding problems
14:30-15:00	Prakash Saivasan, CMI	Games on Multipushdown Systems
15:00-15:30	Tea
15:30-16:00	A V Sreejith, IMSc	Decidability of Presburger arithmetic
16:00-16:30	Ramchandra Phawade, IMSc	Kleene theorems for product systems
16:30-17:00	Ravindra Metta, TRDDC	Statecharts: Specification, Verification environments and limitations
Thursday, 14 July 2011
09:30-10:00	Raj Mohan Matteplackel, IISc	An inductive construction for monitoring automaton for LTL
10:00-11:00	Paritosh Pandya, TIFR	Formal Analysis of Synchronous LSC specifications using logic CTL[DC]
11:00-11:30	Tea
11:30-12:00	K R Raghavendra, IISc	Information-theoretic measures and Program security
12:00-13:00	S P Suresh, CMI	Authorization logics: logical issues
13:00-14:00	Lunch